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timing generator for frame readout ccd image sensor description the CXD2492R is a timing generator ic which generates the timing pulses for performing frame readout using the icx252 ccd image sensor. features base oscillation frequency 24 to 36mhz high-speed/low-speed shutter function draft (sextuple speed)/af (auto focus) drive horizontal driver for ccd image sensor vertical driver for ccd image sensor applications digital still cameras structure silicon gate cmos ic applicable ccd image sensors icx252 (type 1/1.8, 3240k pixels) pin configuration absolute maximum ratings supply voltage v dd v ss ?0.3 to +7.0 v v l ?0.0 to v ss v v h v l ?0.3 to +26.0 v input voltage v i v ss ?0.3 to v dd + 0.3 v output voltage v o1 v ss ?0.3 to v dd + 0.3 v v o2 v l ?0.3 to v ss + 0.3 v v o3 v l ?0.3 to v h + 0.3 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd b 3.0 to 5.5 v v dd a, v dd c, v dd d 3.0 to 3.6 v v m 0.0 v v h 14.5 to 15.5 v v l ?.0 to ?.0 v operating temperature topr ?0 to +75 ? ?1 e99730-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD2492R 48 pin lqfp (plastic) * groups of pins enclosed in the figure indicate sections for which power supply separation is possible. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 h2 v dd 3 v dd 4 xshp xshd xrs pblk clpdm v ss 4 obclp adclk v ss 5 cko cki osco osci v dd 5 mcko ssi sck sen vd hd v ss 6 h1 v ss 3 v ss 2 rg v dd 2 ssgsl v dd 1 wen id sncsl rst v ss 1 test2 sub v3b vl v3a v1b vh v1a v4 v2 vm test1
? 2 CXD2492R block diagram 3 5 3 4 3 9 4 4 4 3 4 1 5 4 2 4 2 3 2 2 2 0 1 9 2 1 1 8 1 7 1 6 1 5 1 0 9 8 1 1 1 3 1 2 1 4 2 8 2 7 2 6 2 5 3 0 v 1 b v 2 v 3 a v 1 a w e n i d v s s 5 a d c l k o b c l p c l p d m p b l k v s s 4 x r s x s h d x s h p v d d 4 v s s 2 r g v d d 2 v s s 3 h 2 h 1 v d d 3 v d h d 7 2 9 1 v s s 1 3 6 v s s 6 v d d 5 v d d 1 m c k o c k o c k i o s c o o s c i p u l s e g e n e r a t o r 2 3 7 4 8 t e s t 2 t e s t 1 r s t 4 5 3 8 4 2 4 7 4 0 4 6 v l v m v h s u b v 4 v 3 b 3 1 3 2 3 3 s e n s c k s s i r e g i s t e r v d r i v e r 6 s s g s l 3 s n c s l 1 / 2 s e l e c t o r s e l e c t o r l a t c h s s g
? 3 CXD2492R pin description gnd internal system reset input. high: normal operation, low: reset control normally apply reset during power-on. schmitt trigger input/no protective diode on power supply side control input used to switch sync system. high: cki sync, low: mcko sync with pull-down resistor vertical direction line identification pulse output. memory write timing pulse output. internal ssg enable. high: internal ssg valid, low: external sync valid with pull-down resistor 3.3v power supply. (power supply for common logic block) 3.3v power supply. (power supply for rg) ccd reset gate pulse output. gnd gnd ccd horizontal register clock output. ccd horizontal register clock output. 3.3 to 5.0v power supply. (power supply for h1/h2) 3.3v power supply. (power supply for cds block) ccd precharge level sample-and-hold pulse output. ccd data level sample-and-hold pulse output. sample-and-hold pulse output for analog/digital conversion phase alignment. pulse output for horizontal and vertical blanking period pulse cleaning. ccd dummy signal clamp pulse output. gnd ccd optical black signal clamp pulse output. clock output for analog/digital conversion ic. logical phase adjustment possible using the serial interface data. gnd inverter output. inverter input. inverter output for oscillation. when not used, leave open or connect a capacitor. inverter input for oscillation. when not used, fix low. 3.3v power supply. (power supply for common logic block) system clock output for signal processing ic. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ss 1 rst sncsl id wen ssgsl v dd 1 v dd 2 rg v ss 2 v ss 3 h1 h2 v dd 3 v dd 4 xshp xshd xrs pblk clpdm v ss 4 obclp adclk v ss 5 cko cki osco osci v dd 5 mcko i i o o i o o o o o o o o o o o i o i o pin no. symbol i/o description
? 4 CXD2492R serial interface data input for internal mode settings. schmitt trigger input/no protective diode on power supply side serial interface clock input for internal mode settings. schmitt trigger input/no protective diode on power supply side serial interface strobe input for internal mode settings. schmitt trigger input/no protective diode on power supply side vertical sync signal input/output. horizontal sync signal input/output. gnd ic test pin 1; normally fixed to gnd. with pull-down resistor gnd (gnd for vertical driver) ccd vertical register clock output. ccd vertical register clock output. ccd vertical register clock output. 15.0v power supply. (power supply for vertical driver) ccd vertical register clock output. ccd vertical register clock output. ?.5v power supply. (power supply for vertical driver) ccd vertical register clock output. ccd electronic shutter pulse output. ic test pin 2; normally fixed to gnd. with pull-down resistor 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ssi sck sen vd hd v ss 6 test1 vm v2 v4 v1a vh v1b v3a vl v3b sub test2 i i i i/o i/o i o o o o o o o i pin no. symbol i/o description
? 5 CXD2492R electrical characteristics dc characteristics (within the recommended operating conditions) v dd2 v dd3 v dd4 v dd1 , v dd5 rst ssi, sck, sen, test1, test2 sncsl, ssgsl vd, hd h1, h2 rg xshp, xshd, xrs, pblk, obclp, clpdm, adclk cko mcko v1a, v1b, v3a, v3b, v2, v4 sub v dd a v dd b v dd c v dd d v t+ v t v t+ v t v ih1 v il1 v ih2 v il2 v ih3 v il3 v oh1 v ol1 v oh2 v ol2 v oh3 v ol3 v oh5 v ol5 v oh6 v ol6 i ol i om1 i om2 i oh i osl i osh 3.0 3.0 3.0 3.0 0.8v dd d 0.8v dd d 0.7v dd d 0.7v dd d 0.8v dd d v dd d ?0.8 v dd b ?0.8 v dd a ?0.8 v dd d ?0.8 v dd d ?0.8 10.0 5.0 5.4 3.3 3.3 3.3 3.3 3.6 5.5 3.6 3.6 0.2v dd d 0.2v dd d 0.2v dd d 0.3v dd d 0.2v dd d 0.4 0.4 0.4 0.4 0.4 ?.0 ?.2 ?.0 v v v v v v v v v v v v v v v v v v v v v v v v ma ma ma ma ma ma feed current where i oh = ?.2ma pull-in current where i ol = 2.4ma feed current where i oh = ?2.0ma pull-in current where i ol = 14.4ma feed current where i oh = ?.3ma pull-in current where i ol = 2.4ma feed current where i oh = ?.9ma pull-in current where i ol = 4.8ma feed current where i oh = ?.3ma pull-in current where i ol = 2.4ma v1a/b, v2, v3a/b, v4 = ?.25v v1a/b, v2, v3a/b, v4 = ?.25v v1a/b, v3a/b = 0.25v v1a/b, v3a/b = 14.75v sub = ?.25v sub = 14.75v supply voltage 1 supply voltage 2 supply voltage 3 supply voltage 4 input voltage 1 * 1 input voltage 2 * 2 input voltage 3 * 3 input voltage 4 * 4 input/output voltage output voltage 1 output voltage 2 output voltage 3 output voltage 4 output voltage 5 output current 1 output current 2 item pins symbol conditions min. typ. max. unit * 1 this input pin is a schmitt trigger input and it does not have protective diode of the power supply side in the ic. * 2 these input pins are schmitt trigger inputs. * 3 these input pins are with pull-down resistor in the ic. * 4 these input pins are with pull-down resistor in the ic and they do not have protective diode of the power supply side in the ic. note) the above table indicates the condition for 3.3v drive. v oh4 v ol4 feed current where i oh = ?.3ma pull-in current where i ol = 2.4ma v dd c ?0.8 0.4 v v
? 6 CXD2492R inverter i/o characteristics for oscillation (within the recommended operating conditions) item logical vth input voltage output voltage feedback resistor oscillation frequency pins osci osci osco osci, osco osci, osco symbol lvth v ih v il v oh v ol rfb f conditions feed current where i oh = ?.6ma pull-in current where i ol = 2.4ma v in = v dd d or v ss min. 0.7v dd d v dd d ?0.8 500k 20 typ. v dd d/2 2m max. 0.3v dd d 0.4 5m 50 unit v v v v v mhz item logical vth input voltage input amplitude pins cki symbol lvth v ih v il v in conditions fmax 50mhz sine wave min. 0.7v dd d 0.3 typ. v dd d/2 max. 0.3v dd d unit v v v vp-p item rise time fall time output noise voltage symbol ttlm ttmh ttlh ttml tthm tthl vclh vcll vcmh vcml conditions vl to vm vm to vh vl to vh vm to vl vh to vm vh to vl min. 200 200 30 200 200 30 typ. 350 350 60 350 350 60 max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 unit ns ns ns ns ns ns v v v v inverter input characteristics for base oscillation clock duty adjustment (within the recommended operating conditions) note) input voltage is the input voltage characteristics for direct input from an external source. input amplitude is the input amplitude characteristics in the case of input through a capacitor. switching characteristics (vh = 15.0v, vm = gnd, vl = ?.5v) notes) 1. the mos structure of this ic has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2. for noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1 f or more) between each power supply pin (vh, vl) and gnd. 3. to protect the ccd image sensor, clamp the sub pin output at vh before input to the ccd image sensor.
? 7 CXD2492R switching waveforms v 1 a ( v 1 b , v 3 a , v 3 b ) v 2 ( v 4 ) s u b t t m h t t h m v h v m v l v m v l v h v l 9 0 % 1 0 % 9 0 % 1 0 % t t l m t t l m 9 0 % 1 0 % 9 0 % 1 0 % t t l h t t h l 9 0 % 9 0 % 1 0 % 1 0 % t t m l 9 0 % 1 0 % t t m l 9 0 % 1 0 % waveform noise v c m h v c m l v h v l v c l h v c l l
? 8 CXD2492R measurement circuit 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 v d c k i c 6 c 6 c 6 c 6 c 6 c 6 c 6 c 6 c 6 c 5 c 5 c 4 c 3 c x d 2 4 9 2 r s e r i a l i n t e r f a c e d a t a h d + 3 . 3 v 7 . 5 v + 1 5 . 0 v c 2 c 2 c 2 c 2 c 2 r 1 r 1 r 1 r 2 r 1 r 1 r 1 c 2 c 2 c 2 c 2 c 2 c 2 c 2 c 2 c 2 c 1 c 1 c 1 c 1 c 1 c 1 c 2 c1 3300pf c2 560pf c3 820pf c4 30pf c5 215pf c6 10pf r1 30 r2 10
? 9 CXD2492R ac characteristics ac characteristics between the serial interface clocks s s i 0 . 2 v d d d 0 . 2 v d d d 0 . 8 v d d d t s 2 t h 1 t s 1 t s 3 0 . 8 v d d d 0 . 8 v d d d s c k s e n s e n symbol t s1 t h1 t s2 t s3 definition ssi setup time, activated by the rising edge of sck ssi hold time, activated by the rising edge of sck sck setup time, activated by the rising edge of sen sen setup time, activated by the rising edge of sck min. typ. max. 20 20 20 20 unit ns ns ns ns serial interface clock internal loading characteristics (1) (within the recommended operating conditions) t h 1 e n l a r g e d v i e w e x a m p l e : d u r i n g f r a m e m o d e 0 . 2 v d d d t s 1 0 . 2 v d d d v 1 a v d h d h d v 1 a s e n 0 . 8 v d d d symbol t s1 t h1 definition sen setup time, activated by the falling edge of hd sen hold time, activated by the falling edge of hd min. typ. max. 0 102 unit ns s * be sure to maintain a constantly high sen logic level near the falling edge of the hd in the horizontal period during which v1a/b and v3a/b values take the ternary value and during that horizontal period. (within the recommended operating conditions)
? 10 CXD2492R serial interface clock output variation characteristics normally, the serial interface data is loaded to the CXD2492R at the timing shown in "serial interface clock internal loading characteristics (1)" above. however, one exception to this is when the data such as stb is loaded to the CXD2492R and controlled at the rising edge of sen. see "description of operation". 0 . 8 v d d d s e n o u t p u t s i g n a l t p d p u l s e symbol tpdpulse definition output signal delay, activated by the rising edge of sen min. typ. max. 100 5 unit ns (within the recommended operating conditions) serial interface clock internal loading characteristics (2) t h 1 e n l a r g e d v i e w 0 . 2 v d d d t s 1 0 . 2 v d d d v d h d v d h d s e n 0 . 8 v d d d e x a m p l e : d u r i n g f r a m e m o d e symbol t s1 t h1 definition sen setup time, activated by the falling edge of vd sen hold time, activated by the falling edge of vd min. typ. max. 0 200 unit ns ns * be sure to maintain a constantly high sen logic level near the falling edge of vd. (within the recommended operating conditions)
? 11 CXD2492R r s t 0 . 2 v d d d t w 1 0 . 8 v d d d v d , h d m c k o t s 1 t h 1 0 . 2 v d d d 0 . 8 v d d d 0 . 2 v d d d rst loading characteristics symbol t w1 definition rst pulse width min. typ. max. 35 unit ns (within the recommended operating conditions) vd and hd loading characteristics symbol t s1 t h1 definition vd and hd setup time, activated by the rising edge of mcko vd and hd hold time, activated by the rising edge of mcko min. typ. max. 20 5 unit ns ns mcko load capacitance = 10pf (within the recommended operating conditions) 0 . 8 v d d d m c k o w e n , i d t p d 1 wen and id load capacitance = 10pf (within the recommended operating conditions) symbol tpd1 definition time until the above outputs change after the rise of mcko min. typ. max. 60 20 unit ns output variation characteristics
? 12 CXD2492R description of operation pulses output from the CXD2492R are controlled mainly by the rst pin and by the serial interface data. the pin status table is shown below, and the details of serial interface control are described on the following pages. pin status table * 1 it is for output. for input, all items are "act". note) act means that the circuit is operating, and dis means that loading is stopped. l indicates a low output level, and h a high output level in the controlled status. also, vh, vm and vl indicate the voltage levels applied to vh (pin 42), vm (pin 38) and vl (pin 45), respectively, in the controlled status. pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 v ss 1 rst sncsl id wen ssgsl v dd 1 v dd 2 rg v ss 2 v ss 3 h1 h2 v dd 3 v dd 4 xshp xshd xrs pblk clpdm v ss 4 obclp adclk v ss 5 act act act act act act act act act act act act act act act act act l l act l l l l l l l l l l act act l l act l l l l l l l l l l l act l l act act act act act act act h h h act 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 cko cki osco osci v dd 5 mcko ssi sck sen vd * 1 hd * 1 v ss 6 test1 vm v2 v4 v1a vh v1b v3a vl v3b sub test2 act act act act act act act act act act act act act act act act act act act act act act act act act l l vm vm vh vh vh vh vh l act act act l act act act l l vm vm vh vh vh vh vh act act act act act dis dis dis h h vm vl vm vm vl vl vl symbol cam slp stb rst pin no. symbol cam slp stb rst
? 13 CXD2492R serial interface control the CXD2492R basically loads and reflects the serial interface data sent in the following format in the readout portion at the falling edge of hd. here, readout portion specifies the horizontal period during which v1a/b and v3a/b, etc. take the ternary value. note that some items reflect the serial interface data at the falling edge of vd or the rising edge of sen. s s i s c k s e n 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 4 1 4 2 4 3 4 4 4 5 4 6 4 7 there are two categories of serial interface data: CXD2492R drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). the details of each data are described below.
? 14 CXD2492R control data data d00 to d07 d08 to d09 d10 to d12 d13 to d14 d15 d16 to d23 d24 to d33 d34 d35 d36 to d37 d38 to d39 d40 to d47 symbol chip ctg mode smd ptsg cdat ldad stb function chip enable category switching drive mode switching electronic shutter mode switching internal ssg output pattern switching af drive control data adclk logic phase switching standby control data = 0 data = 1 10000001 ? enabled other values ? disabled see d08 to d09 ctg. see d10 to d12 mode. see d13 to d14 smd. ntsc equivalent pal equivalent see d16 to d23 cdat. see d36 to d37 ldad. see d38 to d39 stb. rst all 0 all 0 all 0 all 0 0 all 0 all 0 1 0 all 0 all 0 1 0
? 15 CXD2492R shutter data data d00 to d07 d08 to d09 d10 to d19 d20 to d31 d32 to d41 d42 to d47 symbol chip ctg svd shd spl function chip enable category switching electronic shutter vertical period specification electronic shutter horizontal period specification high-speed shutter position specification data = 0 data = 1 10000001 ? enabled other values ? disabled see d08 to d09 ctg. see d10 to d19 svd. see d20 to d31 shd. see d32 to d41 spl. rst all 0 all 0 all 0 all 0 all 0 all 0
? 16 CXD2492R detailed description of each data shared data: d08 to d09 ctg [category] of the data provided to the CXD2492R by the serial interface, the CXD2492R loads d10 and subsequent data to each data register as shown in the table below according to the combination of d08 and d09 . d09 0 0 1 d08 0 1 x description of operation loading to control data register loading to shutter data register test mode note that the CXD2492R can apply these categories consecutively within the same vertical period. however, care should be taken as the data is overwritten if the same category is applied. control data: d10 to d12 mode [drive mode] the CXD2492R drive mode can be switched as follows. however, the drive mode bits are loaded to the CXD2492R and reflected at the falling edge of vd. d11 0 0 1 1 0 1 d12 0 0 0 0 1 1 d10 0 1 0 1 x x description of operation draft mode (sextuple speed: default) frame mode (a field readout) frame mode (b field readout) frame mode af1 mode af2 mode control data: d15 ptsg [internal ssg output pattern] the CXD2492R internal ssg output pattern can be switched as follows. however, the drive mode bits are loaded to the CXD2492R and reflected at the falling edge of vd. d15 0 1 description of operation ntsc equivalent pattern pal equivalent pattern vd period in each pattern is defined as follows. * 1 only 944h and 945h are 1208ck period. see the timing charts for the actual operation. ntsc equivalent pattern pal equivalent pattern frame mode 918h + 1716ck 945h * 1 draft mode 262h + 1144ck 314h + 1568ck af1 mode 131h + 572ck 157h + 784ck af2 mode 65h + 1430ck 78h + 1536ck
? 17 CXD2492R control data: d36 to d37 ldad [adclk logic phase] this indicates the adclk logic phase adjustment data. the default is 90 relative to mcko. control data: d38 to d39 stb [standby] the operating mode is switched as follows. however, the standby bits are loaded to the CXD2492R and control is applied immediately at the rising edge of sen. d37 0 0 1 1 d36 0 1 0 1 degree of adjustment ( ) 0 90 180 270 d39 x 0 1 d38 0 1 1 symbol cam slp stb operating mode normal operating mode sleep mode standby mode see the pin status table for the pin status in each mode.
? 18 CXD2492R the frame shift data is expressed as shown in the table below using d16 to d23 cdat. msb lsb d23 d22 d21 d20 d19 d18 d17 d16 0 1 1 0 6 1 0 0 1 9 ? cdat is expressed as 69h . its definition area is specified as follows. af1 mode: 00h cdat ffh (11 to 23h) af2 mode: 00h cdat ffh (14 to 27h) control data: [af drive] the CXD2492R controls the drive of the vertical cut-out area of line in af1/af2 mode by using control data d16 to d23 cdat. this mode has a function on purpose to raise frame rate for auto focus (af), and this mode cannot support operation such as electrical image stabilization. af drive bits are loaded to the CXD2492R and reflected at the falling edge of vd. as shown in the figure below, first, the fixed stage is swept at high speed, and it goes to readout period and vertical ob period. then normal transfer is performed equivalent to draft mode from the frame shift of the stage specified by the serial interface data to the timing of the falling edge of the next vd. therefore, the number of frame shift stages applied to cdat and the control by vd period are conditions for its application. vd 0 v1a vck mode 00h ffh cdat 4 0 00h frame shift normal transfer high-speed sweep the number of high-speed sweeps are different according to the selected mode. it is specified as follows. af1 mode: 138 stages (0 to 7h) af2 mode: 208 stages (0 to 11h)
? 19 CXD2492R control data/shutter data: [electronic shutter] the CXD2492R realizes various electronic shutter functions by using control data d13 to d14 smd and shutter data d10 to d19 svd, d20 to d31 shd and d32 to d41 spl. these functions are described in detail below. first, the various modes are shown below. these modes are switched using control data d13 to d14 smd. d14 0 0 1 1 d13 0 1 0 1 description of operation electronic shutter stopped mode high-speed/low-speed shutter mode htsg control mode the electronic shutter data is expressed as shown in the table below using d20 to d31 shd as an example. however, msb (d31) is a reserve bit for the future specification, and it is handled as dummy on this ic. ? shd is expressed as 1c3h . [electronic shutter stopped mode] during this mode, all shutter data items are invalid. sub is not output in this mode, so the shutter speed is the accumulation time for one field. [high-speed/low-speed shutter mode] during this mode, the shutter data items have the following meanings. the period during which svd and shd are specified together is the shutter speed. concretely, when specifying high-speed shutter, svd is set to "000h". (see the figure.) during low-speed shutter, or in other words when svd is set to "001h" or higher, the serial interface data is not loaded until this period is finished. the vertical period indicated here corresponds to one field in each drive mode. in addition, the number of horizontal periods applied to shd can be considered as (number of sub pulses 1). however, in the frame mode a field, it matches (number of sub pulses + 1). this is a specification for flickerless when the same mode is repeated. but this change may not occur because of flickerless by the conditions during low-speed shutter. note) the bit data definition area is assured in terms of the CXD2492R functions, and does not assure the ccd characteristics. symbol svd shd spl data d10 to d19 d20 to d31 d32 to d41 description number of vertical periods specification (000h svd 3ffh) number of horizontal periods specification (000h shd 7ffh) vertical period specification for high-speed shutter operation (000h spl 3ffh) msb lsb d29 d28 d31 d30 d27 d26 d25 d24 d23 d22 d21 d20 1 1 0 0 c x 0 0 1 1 0 0 1 1 3
? 20 CXD2492R v d s h d 0 1 v 1 a s u b w e n s m d 0 0 0 h 0 0 2 h s v d 0 5 0 h 1 0 f h s h d 0 1 s v d v d s p l s h d 0 1 v 1 a s u b w e n s m d 0 0 0 h 0 0 1 h s p l 0 0 0 h 0 0 2 h s v d 0 a 3 h 1 0 f h s h d 1 0 s v d further, spl can be used during this mode to specify the sub output at the desired vertical period during the low-speed shutter period. in the case below, sub is output based on shd at the spl vertical period out of (svd + 1) vertical periods. incidentally, spl is counted as "000h", "001h", "002h" and so on in conformance with svd. using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice versa.
? 21 CXD2492R v d v 1 a s u b w e n 0 1 1 1 e x p o s u r e t i m e 0 1 s m d v c k [htsg control mode] during this mode, all shutter data items are invalid. the v1a/b and v3a/b ternary level outputs are stopped, so the shutter speed is the value obtained by adding the shutter speed specified in the preceding vertical period to the vertical period during which these readout pulses are stopped as shown in the figure.
? 22 CXD2492R chart-1 vertical direction timing chart mode frame mode applicable ccd image sensor ?icx252 v d s u b o b c l p c l p d m v 1 a c h i g h - s p e e d s w e e p b l o c k h i g h - s p e e d s w e e p b l o c k c v 1 b v 2 v 3 a v 3 b v 4 c c d o u t 1 5 4 7 1 5 4 9 1 5 4 2 1 5 4 4 1 5 4 6 1 5 4 8 1 5 5 0 1 5 3 9 1 5 4 1 1 5 4 3 1 5 4 5 3 1 5 7 2 4 6 8 2 6 4 8 1 0 1 2 1 3 5 7 9 1 1 1 3 1 5 p b l k i d w e n a f i e l d b f i e l d h d 9 1 8 1 2 9 3 4 1 2 8 3 4 9 1 8 8 1 0 8 1 0 a b * the number of sub pulses is determined by the serial interface. this chart shows the case where sub pulses are output in each h orizontal period. * id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. * vd of this chart is ntsc equivalent pattern (918h + 1716ck units). for pal equivalent pattern, it is 945h units, but 1208ck per iod as for 944h and 945h.
? 23 CXD2492R chart-2 vertical direction timing chart mode draft mode applicable ccd image sensor ?icx252 v d h d s u b v 1 a v 2 v 3 a v 3 b v 4 o b c l p c l p d m i d p b l k v 1 b c c d o u t 1 5 1 0 3 6 2 2 2 7 3 4 1 3 8 1 4 2 0 5 4 6 5 3 9 5 3 4 5 2 7 5 4 4 5 3 7 5 3 2 5 2 5 5 4 9 2 5 3 2 1 0 3 6 1 5 2 2 2 7 3 4 8 1 4 1 3 2 0 2 5 3 2 5 4 6 5 3 9 5 3 4 5 2 7 5 4 4 5 3 7 5 3 2 5 2 5 5 4 9 w e n 2 1 2 6 2 2 6 1 2 1 2 6 2 2 6 1 d d * the number of sub pulses is determined by the serial interface. this chart shows the case where sub pulses are output in each h orizontal period. * id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. * vd of this chart is ntsc equivalent pattern (262h + 1144ck units). for pal equivalent pattern, it is 314h + 1568ck units.
? 24 CXD2492R chart-3 vertical direction timing chart mode af1 mode applicable ccd image sensor ?icx252 v d c c d o u t 6 4 6 4 w e n h d i d o b c l p c l p d m p b l k v 1 a v 1 b v 2 v 3 b v 4 s u b v 3 a 1 0 2 5 1 8 1 3 1 1 0 2 5 1 8 1 3 1 f r a m e s h i f t b l o c k f d g f r a m e s h i f t b l o c k f d g h i g h - s p e e d s w e e p b l o c k h i g h - s p e e d s w e e p b l o c k * the number of sub pulses is determined by the serial interface. this chart shows the case where sub pulses are output in each h orizontal period. * id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. * 138 stages are fixed for high-speed sweep block; 0 to 255 stages are specified by the serial interface for frame shift block. * vd of this chart is ntsc equivalent pattern (131h + 572ck units). for pal equivalent pattern, it is 157h + 784ck units.
? 25 CXD2492R chart-4 vertical direction timing chart mode af2 mode applicable ccd image sensor ?icx252 v d c c d o u t 6 4 6 4 w e n h d i d o b c l p c l p d m p b l k v 1 a v 1 b v 2 v 3 b v 4 s u b v 3 a f h i g h - s p e e d s w e e p b l o c k f r a m e s h i f t b l o c k d g f h i g h - s p e e d s w e e p b l o c k f r a m e s h i f t b l o c k d g 1 4 2 9 1 1 2 6 5 1 4 2 9 1 1 2 6 5 * the number of sub pulses is determined by the serial interface. this chart shows the case where sub pulses are output in each h orizontal period. * id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. * 208 stages are fixed for high-speed sweep block; 0 to 255 stages are specified by the serial interface for frame shift block. * vd of this chart is ntsc equivalent pattern (65h + 1430ck units). for pal equivalent pattern, it is 78h + 1536ck units.
? 26 CXD2492R chart-5 horizontal direction timing chart mode frame mode applicable ccd image sensor ?icx252 1 4 8 h d m c k o h 1 h 2 v 1 a / b v 2 v 3 a / b v 4 s u b p b l k o b c l p c l p d m ( 2 2 2 8 ) 0 5 0 5 2 1 0 0 1 5 0 1 1 0 7 0 9 9 4 7 1 0 1 7 4 9 0 5 2 7 0 2 0 0 2 5 0 i d w e n 1 9 8 1 7 2 1 9 8 1 5 7 1 2 8 1 1 0 1 1 0 1 3 8 5 2 * the hd of this chart indicates the actual CXD2492R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. * the hd fall period should be between approximately 2.9 to 9.5 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s). internal ssg is at the timing. * sub is output at the timing shown above when output is controlled by the serial interface data. * id and wen are output at the timing shown above at the position shown in chart-1.
? 27 CXD2492R chart-6 horizontal direction timing chart mode draft/af1/af2 mode applicable ccd image sensor ?icx252 h d m c k o h 1 h 2 v 1 a / b v 2 v 3 a / b v 4 s u b p b l k o b c l p c l p d m ( 2 2 2 8 ) 0 5 0 5 2 1 0 0 1 5 0 7 1 5 2 1 0 9 9 0 1 4 7 6 4 4 7 1 0 1 7 4 5 2 2 0 0 2 5 0 i d w e n 1 9 8 1 7 2 1 9 8 8 3 1 2 1 1 4 0 7 1 1 1 0 1 1 0 1 4 0 5 2 9 0 1 2 8 8 3 1 0 2 1 4 0 1 5 9 1 0 9 1 4 7 1 0 2 1 5 9 1 2 8 1 2 1 6 4 7 1 * the hd of this chart indicates the actual CXD2492R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. * the hd fall period should be between approximately 2.9 to 9.5 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s). internal ssg is at the timing. * sub is output at the timing shown above when output is controlled by the serial interface data. * id and wen are output at the timing shown above at the position shown in chart-2, 3 and 4.
? 28 CXD2492R chart-7 horizontal direction timing chart (high-speed sweep: c) mode frame mode applicable ccd image sensor ?icx252 h d m c k o h 1 h 2 v 1 a / b v 2 v 3 a / b v 4 s u b p b l k o b c l p c l p d m ( 2 2 2 8 ) 0 5 0 5 2 1 0 0 1 5 0 5 2 1 3 9 1 1 0 1 9 7 7 1 7 0 2 0 0 2 5 0 i d w e n 1 7 2 1 0 0 1 2 9 1 3 8 5 2 8 1 1 0 0 1 2 9 1 1 0 1 6 8 1 8 7 2 7 4 1 5 8 1 6 8 2 2 6 1 5 8 1 3 9 # 4 # 3 # 2 # 1 8 1 2 5 5 2 7 4 2 4 5 2 1 6 1 8 7 7 1 2 1 6 2 4 5 1 9 7 2 5 5 2 2 6 * the hd of this chart indicates the actual CXD2492R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. * the hd fall period should be between approximately 2.9 to 9.5 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s). internal ssg is at the timing. * sub is output at the timing shown above when output is controlled by the serial interface data. * high-speed sweep of v1a/b, v2, v3a/b and v4 is performed up to 26h of 768ck (#1038).
? 29 CXD2492R chart-8 horizontal direction timing chart (high-speed sweep: f) (frame shift: g) mode af1/af2 mode applicable ccd image sensor ?icx252 h d m c k o h 1 h 2 v 1 a / b v 2 v 3 a / b v 4 s u b p b l k o b c l p c l p d m ( 2 2 2 8 ) 0 5 0 5 2 1 0 0 1 5 0 7 1 5 2 1 0 9 9 0 1 4 7 6 4 4 7 1 0 5 2 2 0 0 2 5 0 i d w e n 1 7 2 8 3 1 2 1 1 4 0 7 1 1 0 5 1 1 0 1 4 0 5 2 9 0 1 2 8 8 3 1 0 2 1 4 0 1 5 9 1 9 7 2 5 4 1 0 9 1 4 7 1 6 6 1 0 2 1 5 9 1 7 8 2 1 6 2 2 3 2 6 1 2 8 0 2 7 3 1 2 8 2 0 4 2 4 2 1 2 1 2 3 5 2 7 3 2 6 1 2 1 6 2 2 3 1 7 8 1 8 5 1 6 6 6 4 1 8 5 2 0 4 2 4 2 1 9 7 # 2 # 1 2 3 5 2 5 4 2 1 9 7 1 * the hd of this chart indicates the actual CXD2492R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. * the hd fall period should be between approximately 2.9 to 9.5 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s). internal ssg is at the timing. * sub is output at the timing shown above when output is controlled by the serial interface data. * wen are output at the timing shown above at the position shown in chart-3 and 4. * high-speed sweep of v1a/b, v2, v3a/b and v4 is performed up to 6h of 2056ck (#138) in af1 mode and 10h of 884ck (#208) in af2 m ode. * frame shift of v1a/b, v2, v3a/b and v4 receives the output control by the serial interface data and it can specify up to #255 f or both of af1/af2 mode. * id is output at the timing shown with dotted line during frame shift.
? 30 CXD2492R chart-9 horizontal direction timing chart mode frame mode applicable ccd image sensor ?icx252 h d [ a f i e l d ] [ b f i e l d ] [ a ] [ b ] v 3 b v 4 v 3 b v 4 v 1 a v 1 b v 2 v 3 a v 1 a v 1 b v 2 v 3 a ( 2 2 8 8 ) 0 5 2 7 0 1 1 0 9 0 1 2 8 9 9 1 4 8 1 5 7 1 8 1 2 1 1 2 4 1 ( 2 2 8 8 ) 0 5 2 7 0 1 2 8 9 0 1 4 8 9 9 1 1 0 1 5 7 1 1 0 0 1 1 3 0 1 1 6 0 1 1 9 0 1 2 8 0 1 3 1 0 1 2 5 0 l o g i c a l i g n m e n t p o r t i o n * the hd of this chart indicates the actual CXD2492R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. * the hd fall period should be between approximately 2.9 to 9.5 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s). internal ssg is at the timing.
? 31 CXD2492R chart-10 horizontal direction timing chart mode draft /af1/af2 mode applicable ccd image sensor ?icx252 h d [ d ] v 3 b v 4 v 1 a v 1 b v 2 v 3 a ( 2 2 8 8 ) 0 5 2 6 4 1 0 2 1 0 9 7 1 1 2 1 8 3 9 0 1 2 8 1 4 0 1 4 7 1 5 9 ( 2 2 8 8 ) 0 5 2 6 4 1 0 9 8 3 9 0 7 1 1 2 1 1 0 2 1 2 8 1 4 0 1 4 7 1 5 9 1 1 3 0 1 1 6 0 1 1 9 0 1 0 1 0 1 0 4 0 1 0 7 0 1 1 0 0 1 2 2 0 1 2 5 0 1 2 8 0 1 3 1 0 1 3 4 0 1 3 7 0 1 4 0 0 1 4 3 0 * the hd of this chart indicates the actual CXD2492R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. * the hd fall period should be between approximately 2.9 to 9.5 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s). internal ssg is at the timing.
? 32 CXD2492R chart-11 high-speed phase timing chart mode applicable ccd image sensor ?icx252 h d h d ' c k i c k o a d c l k m c k o h 1 h 2 r g x s h p x s h d x r s 1 7 2 5 2 1 * hd' indicates the hd which is the actual CXD2492R load timing. * the phase relationship of each pulse shows the logical position relationship. for the actual output waveform, a delay is added to each pulse. * the logical phase of adclk can be specified by the serial interface data.
? 33 CXD2492R chart-12 vertical direction sequence chart mode draft ? frame ? draft applicable ccd image sensor ?icx252 v d v 1 a v 1 b v 2 v 3 a v 3 b v 4 s u b m e c h a n i c a l s h u t t e r e x p o s u r e t i m e c c d o u t m o d e s m d s h d c l o s e o p e n a b c e e f 0 0 0 0 0 3 3 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 5 0 h 0 5 0 h 0 5 0 h 0 5 0 h 0 5 0 h 0 0 0 h 0 0 0 h 0 5 0 h 0 5 0 h a b c d e f * this chart is a drive timing chart example of electronic shutter normal operation. * data exposed at d includes blooming component. for details, see ccd image sensor specification. * CXD2492R does not generate the pulse to control mechanical shutter operation. * the switching timing of drive mode and electronic shutter data is not the same.
? 34 CXD2492R application circuit block diagram 2 6 2 7 3 7 4 8 3 1 3 2 3 4 3 5 3 0 2 5 2 3 2 2 2 0 1 9 1 8 1 7 1 6 m c k o v d h d c k o 1 0 d 0 t o 9 a d c l k o b c l p c l p d m p b l k x r s x s h d x s h p s c k 3 3 s e n s s i t e s t 2 t e s t 1 o s c o c k i 2 8 o s c i c c d o u t v - d r v r t d r v o u t v r b 6 3 2 5 4 s s g s l s n c s l r s t w e n i d 1 2 1 3 9 r g h 2 h 1 4 1 4 3 3 9 v 2 v 1 b v 1 a 4 4 4 6 4 0 v 4 4 7 s u b v 3 b v 3 a c c d i c x 2 5 2 s / h c x a 2 0 0 6 q t g c x d 2 4 9 2 r a / d c x d 2 3 1 1 a r c o n t r o l l e r s i g n a l p r o c e s s o r b l o c k notes for power-on of the three ?.5v, +15.0v and +3.3v power supplies, be sure to start up the ?.5v and +15.0v power supplies in the following order to prevent the sub pin of the ccd image sensor from going to negative potential. t 1 t 2 1 5 . 0 v 0 v 7 . 5 v 2 0 % 2 0 % t 2 3 t 1 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 35 CXD2492R s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n p l a t i n g 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e 4 8 p i n l q f p ( p l a s t i c ) 9 . 0 0 . 2 * 7 . 0 0 . 1 1 1 2 1 3 2 4 2 5 3 6 3 7 4 8 ( 0 . 2 2 ) 0 . 1 8 0 . 0 3 + 0 . 0 8 0 . 2 g l q f p - 4 8 p - l 0 1 l q f p 0 4 8 - p - 0 7 0 7 ( 8 . 0 ) 0 . 5 0 . 2 0 . 1 2 7 0 . 0 2 + 0 . 0 5 a 1 . 5 0 . 1 + 0 . 2 0 . 1 s o l d e r / p a l l a d i u m n o t e : d i m e n s i o n * d o e s n o t i n c l u d e m o l d p r o t r u s i o n . 0 . 1 0 . 1 0 . 5 0 . 2 0 t o 1 0 d e t a i l a 0 . 1 3 m 0 . 5 s s b d e t a i l b : s o l d e r ( 0 . 1 8 ) ( 0 . 1 2 7 ) d e t a i l b : p a l l a d i u m 0 . 1 2 7 0 . 0 4 0 . 1 8 0 . 0 3 + 0 . 0 8 0 . 1 2 7 0 . 0 2 + 0 . 0 5 0 . 1 8 0 . 0 3 package outline unit: mm

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